Andrew P. Clarke

Consultant overview

Andy Clarke is a technologist with more than 35 years experience developing reliable advanced products and processes. His work has resulted in more than 20 patents, 40 critical trade secret filings and over a dozen published papers and technology awards. His experience has helped him hone an expert-level skill set across a spectrum of useful applications.

He has helped clients and past employers with product design, equipment selection, manufacturing problems, trade secrets and patent disputes, often by identifying simple low-cost solutions.

Areas of expertise

Andy helps his clients solve challenges that are limiting their ability be profitable. He is most often engaged by manufacturers of semiconductor and MEMS devices, providers of thin film services or processing equipment or attorneys seeking his advice or involvement as an expert witness. His areas of expertise include the following:

• Vacuum process technology — process development and integration, equipment selection and physics-based analysis of systems
• Process reliability and yield — root-cause failure analysis, yield improvement, and cycle time reduction
• Capital equipment analysis and selection — tool evaluation, acceptance, technology roadmaps, budgets, and program timelines
• Patent services — patentability analysis, including prior art research and comparison, and patent specification writing
• Expert witness engagements — experienced expert witness in trade secret disputes, and declaration writing for ex parte patent reexaminations

Getting started

Andy brings practical experience, technical depth, and a fresh point of view to help identify the root cause and develop an effective path forward.

Schedule a free 20-minute telephone consultation to discuss your situation. If the problem is a good fit for Andy’s expertise, he will provide his rates, terms, and availability.

Confidentiality: All communication is handled with absolute discretion.

Selected experience

PVD Technology Director, Plasma-Therm LLC (2023–2026) Managed product development for two PVD product lines.

Senior Principal Engineer, Raytheon (2013–2023) Developed manufacturable processes for detector and IC integration, improving yield and performance through innovation and failure analysis.

Technology Consultant & Expert Witness (2006–2013) Delivered manufacturing, process, materials and equipment solutions; served as expert witness in patent and trade secret litigation.

VP & General Manager, PVD Products Division, Tegal Corporation (2004–2006)

Founder & CEO, First Derivative Systems, Inc. (1999–2004)

Senior Engineering VP, Sputtered Films, Inc. (1989–1999)

US DOE Graduate Fellow, Center for Materials Science, Los Alamos National Laboratory (1987–1989)

Education

• MS (USU) and BS (UCSB), Physics

Reference Patent List

• 5,135,634 Bias capable water-cooled “Lens Shield” for the S-Gun to improve the uniformity of ion bombardment during bias sputtering.
• 5,766,426 Optical sight tube S-Gun anode and temperature feedback loop to allow real-time measurement of film temperature and control backside IR heating during deposition.
• 6,086,947 212 TiN Barrier Film: a film sandwich comprising brown “Zone 1” TiN between two layers of gold “Zone 2” TiN to effectively lengthen the diffusion path and reduce reactions between aluminum and silicon.
• 6,235,656 Method patent for the MDT Dual Degas/Cool Single-wafer Loadlock, describing the process of degassing a wafer during pumpdown, and cooling wafers during vent from vacuum to atmosphere in a single-wafer loadlock.
• 6,562,141 Device patent for the MDT Dual Degas/Cool Single-wafer Loadlock, describing the hardware design.
• 6,605,198 Device patent for the biasable S-Gun anode.
• 6,830,664 Magnetically enhanced hollow cathode array sputter source for generating a uniform flux of ionized metal atoms.
• 8,663,389 Membrane Assisted Semi-Closed (MASC) Reactor for HVPE growth of GaN, utilizing a hydrogen permeable membrane.
• 10,515,905 SiN stress compensation layer
• 11,101,130 Filling Vias with Eutectic Compositions
• 11,410,937 AlN stress buffer layer for HgCdTe bonding oxide deposition
• 11,659,660 Oxide TGV stress buffer liner to avoid glass substrate cracking
• 11,817,521 Non-Gold P-type Si contact intermediary between formed NiSi and HgCdTe
• 11,851,785 AlN passivation for HgCdTe device to prevent Hg loss and performance degradation
• 11,854,879 Cu3Sn via metallization for TSV fusion bond
• 11,894,477AlN stress buffer and stress compensation for wafer bonding to HgCdTe layers in 3D integration
• 12,002,773 Hybrid Pocket Post for vertical interconnect in 3D Integration
• 12,354,911 Division of 11,854,879 B2: Cu3Sn via metallization for TSV fusion bond
• 12,593,525 Offset Vertical Interconnect for 3D wafer Integration with HgCdTe
• 12,684,896 Integrated 3D MCT Wafer Process Incorporating AlN Stress and Buffer Layers